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1 ? fn6461.0 isl54054, ISL54055 ultra low on-resistan ce, low voltage, single supply, si ngle spst/1:2 distribution analog switch the intersil isl54054 and ISL54055 devices consist of low on-resistance, low voltage, bi-directional spst analog switches designed to operate from a single +1.8v to +5.5v supply. these devices have an unique architecture. they have two signal pins (pin 1 and pin 3) that are simultaneously connected or disconnected to a common pin (pin 4) under the control of a single logic control pin (pin 6). the isl54054 switches are off when the logic is low and on when the logic is high. the ISL54055 switches are on when the logic is low and off when the logic is high. this architecture allows these devices to be used as a single spst switch or as a distributi on switch to di stribute a single source to two different loads. spst operation is achieved by us ing one of the signal pins while floating the other signal pi n or by externally connecting the two signal pins together. when both signal pins are tied together, the r on of the spst is reduced by half, from 1 to 0.5 (when operated with a 5v supply). targeted applications incl ude battery powered equipment that benefit from low r on resistance, excellent r on flatness, and fast switching speeds (t on = 12ns, t off = 12ns). the digital logic input is 1.8v logic compatible when using a single 2.7v to +3.6v supply and ttl compatible when the supply is > +3.6v. the isl54054 and the ISL54055 are offered in a 6 ld 1.2mmx1.0mmx0.5mm tdfn package, alleviating board space limitations. the isl54054 has two normally open (no) switches and the ISL54055 has two normally closed (nc) switches. features ? on-resistance (r on ) (signal pins connected) -v cc = +5.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.34 -v cc = +3.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.51 -v cc = +1.8v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 ?r on flatness (+4.5v supply) . . . . . . . . . . . . . . . . . . . . . 0.13 ? single supply operation . . . . . . . . . . . . . . . . . +1.8v to +5.5v ? fast switching action (+4.5v supply) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns ? esd hbm rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kv ? 1.8v logic compatible (+3v supply) ? available in 6 lead tdfn package ? pb-free plus anneal available (rohs compliant) applications ? battery powered, handheld and portable equipment - cellular/mobile phones - pagers - laptops, notebooks, palmtops ? portable test and measurement ? medical equipment ? audio and video switching related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensit ive surface mount devices (smds)? table 1. features at a glance isl54054 ISL54055 number of switches 11 sw no nc 1.8v r on 1.1 1.1 1.8v t on /t off 115ns/90ns 115ns/90ns 3v r on 0.51 0.51 3v t on /t off 22ns/17ns 22ns/17ns 5v r on 0.34 0.34 5v t on /t off 12ns/12ns 12ns/12ns packages 6 ld tdfn ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl54054iruz-t d -40 to +85 6 ld tdfn tape and reel l6.1.2x1.0a ISL54055iruz-t e -40 to +85 6 ld tdfn tape and reel l6.1.2x1.0a note: intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are ro hs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet march 21, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6461.0 march 21, 2007 pinouts (note 1) isl54054 (6 ld tdfn) top view ISL54055 (6 ld tdfn) top view note: 1. switches shown for logic ?0? input. 3 2 1 6 5 4 in v+ gnd no no com 3 2 1 6 5 4 in v+ gnd nc nc com truth table logic isl54054 both no switches ISL54055 both nc switches 0offon 1onoff note: logic ?0? 0.5v. logic ?1? 1.4v with a 3v supply. pin descriptions pin function v+ system power supply input (+1.8v to +5.5v) gnd ground connection in digital control input com analog switch common pin no analog switch normally open pin nc analog switch normally closed pin isl54054, ISL54055
3 fn6461.0 march 21, 2007 absolute maximum rati ngs thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.0v input voltages no, nc, in (note 2). . . . . . . . . . . . . . . . . . . . . -0.5 to ((v+) + 0.5v) output voltages com (note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((v+) + 0.5v) continuous current no, nc, or com . . . . . . . . . . . . . . . . . 300ma peak current no, nc, or com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . . . . . 600ma esd rating human body model (per mil-std-883 method 3015.7) . . . .>6kv machine model (per eiaj ed-4701 method c-111) . . . . . . .>200v charged device model (per eos/esd ds5.3, 4/14/93) . .>1000v operating conditions v+ (positive dc supply voltage) . . . . . . . . . . . . . . . . . 1.8v to 5.5v analog signal range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to v+ v in (digital logic input voltage (in). . . . . . . . . . . . . . . . . . 0v to v+ temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance (typical, note 3) ja (c/w) 6 ld tdfn package . . . . . . . . . . . . . . . . . . . . . . . 175 maximum junction temperature (plastic package). . . . . . . +150c maximum storage temperature range . . . . . . . . . . . -65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . +300c (lead tips only) pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 2. signals on nc, no, in, or com exceeding v+ or gnd are clamped by internal diodes. limit forward diode current to maximum curr ent ratings. 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (notes 4, 6), unless otherwise specified parameter test conditions temp (c) (note 5) min typ (note 5) max units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on (nx inputs connected) v+ = 4.5v, i com = 100ma, v no or v nc = 0v to v+, (see figure 4) 25 - 0.36 - full - 0.49 - r on flatness, r flat(on) (nx inputs connected) v+ = 4.5v, i com = 100ma, v no or v nc = 0v to v+, (note 7) 25 - 0.12 - full - 0.13 - on-resistance, r on (single nx input) v+ = 4.5v, i com = 100ma, v no or v nc = 0v to v+, (see figure 4) 25 - 0.85 - full - 1.1 - r on flatness, r flat(on) (single nx input) v+ = 4.5v, i com = 100ma, v no or v nc = 0v to v+, (note 7) 25 - 0.25 - full - 0.25 - no or nc off leakage current, i no(off) or i nc(off) v+ = 5.5v, v com = 0.3v, 5v, v no or v nc = 5v, 0.3v 25 -10 5 10 na full -150 - 150 na com on leakage current, i com(on) v + = 5.5v, v com = 0.3v, 5v, or v no or v nc = 0.3v, 5v, or floating 25 -20 9 20 na full -300 - 300 na dynamic characteristics turn-on time, t on v+ = 4.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 1) 25 - 12 - ns full - 15 - ns turn-off time, t off v+ = 4.5v, v no or v nc = 3.0v, r l = 50 , c l = 35pf (see figure 1) 25 - 12 - ns full - 15 - ns charge injection, q v g = 0v, r g = 0 , c l = 1.0nf (see figure 2) 25 - 71 - pc off isolation (nx inputs connected) r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 3) 25 - 74 - db off isolation (single nx input) r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 3) 25 - 83 - db isl54054, ISL54055
4 fn6461.0 march 21, 2007 -3db bandwidth (nx inputs connected) r l = 50 25 - 72 - mhz -3db bandwidth (single nx input) r l = 50 25 - 138 - mhz no or nc off capacitance, c off (nx inputs connected) f = 1mhz, v no or v nc = v com = 0v (see figure 5) 25 - 30 - pf com on capacitance, c com(on) (nx inputs connected) f = 1mhz, v no or v nc = v com = 0v (see figure 5) 25 - 62 - pf no or nc off capacitance, c off (single nx input) f = 1mhz, v no or v nc = v com = 0v (see figure 5) 25 - 16 - pf com on capacitance, c com(on) (single nx input) f = 1mhz, v no or v nc = v com = 0v (see figure 5) 25 - 89 - pf power supply characteristics power supply range full 1.8 - 5.5 v positive supply current, i+ v+ = 5.5v, v in = 0v or v+ 25 - - 0.5 a full - - 1.0 a digital input characteristics input voltage low, v inl full - - 0.8 v input voltage high, v inh full 2.4 - - v input current, i inh , i inl v+ = 5.5v, v in = 0v or v+ full -1 - 1 a electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.6v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (notes 4, 6), unless otherwise specified parameter test conditions temp (c) (note 5) min typ (note 5) max units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on (nx inputs connected) v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (see figure 4) 25 - 0.57 0.65 full - 0.73 1.0 r on flatness, r flat(on) (nx inputs connected) v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (note 7) 25 - 0.2 0.4 full - 0.2 0.5 on-resistance, r on (single nx input) v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (see figure 4) 25 - 1.3 1.7 full - 1.6 2.0 r on flatness, r flat(on) (single nx input) v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (note 7) 25 - 0.4 0.6 full - 0.4 0.7 dynamic characteristics turn-on time, t on v+ = 2.7v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1) 25 - 22 - ns full - 25 - ns turn-off time, t off v+ = 2.7v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1) 25 - 17 - ns full - 20 - ns charge injection, q v g = 0v, r g = 0 , c l = 1.0nf (see figure 2) 25 - 42 - pc off isolation (nx inputs connected) r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 3) 25 - 74 - db off isolation (single nx input) r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms (see figure 3) 25 - 83 - db no or nc off capacitance, c off (nx inputs connected) f = 1mhz, v no or v nc = v com = 0v (see figure 5) 25 - 30 - pf electrical specifications - 5v supply test conditions: v+ = +4.5v to +5.5v, gnd = 0v, v inh = 2.4v, v inl = 0.8v (notes 4, 6), unless otherwise specified (continued) parameter test conditions temp (c) (note 5) min typ (note 5) max units isl54054, ISL54055
5 fn6461.0 march 21, 2007 com on capacitance, c com(on) (nx inputs connected) f = 1mhz, v no or v nc = v com = 0v (see figure 5) 25 - 62 - pf no or nc off capacitance, c off (single nx input) f = 1mhz, v no or v nc = v com = 0v (see figure 5) 25 - 16 - pf com on capacitance, c com(on) (single nx input) f = 1mhz, v no or v nc = v com = 0v (see figure 5) 25 - 89 - pf digital input characteristics input voltage low, v inl full - - 0.5 v input voltage high, v inh full 1.4 - - v input current, i inh , i inl v+ = 3.6v, v in = 0v or v+ full -1 - 1 a electrical specifications - 1.8v supply test conditions: v+ = +1.8v, gnd = 0v, v inh = 1.8v, v inl = 0v (notes 4, 6), unless otherwise specified parameter test conditions temp (c) (note 5) min typ (note 5) max units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on (nx inputs connected) v+ = 1.8v, i com = 100ma, v no or v nc = 0v to v+, pins 1 and 3 connected, (see figure 4) 25 - 1.1 - full - 1.3 - on-resistance, r on (single nx input) v+ = 1.8v, i com = 100ma, v no or v nc = 0v to v+ (see figure 4) 25 - 2.3 - full - 2.53 - dynamic characteristics turn-on time, t on v+ = 1.8v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1) 25 - 115 - ns full - 246 - ns turn-off time, t off v+ = 1.8v, v no or v nc = 1.5v, r l = 50 , c l = 35pf (see figure 1) 25 - 90 - ns full - 192 - ns charge injection, q v g = 0v, r g = 0 ,c l = 1.0nf (see figure 2) 25 - 22 - pc notes: 4. v in = input voltage to perform proper function. 5. the algebraic convention, whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. 6. parts are 100% tested at +25c. limits across the full temperature range are guaranteed by design and correlation. 7. flatness is defined as the difference between maximum and minimum value of on-resi stance over the specified analog signal ran ge. electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.6v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (notes 4, 6), unless otherwise specified (continued) parameter test conditions temp (c) (note 5) min typ (note 5) max units isl54054, ISL54055
6 fn6461.0 march 21, 2007 test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times figure 2a. measurement poin ts figure 2b. test circuit figure 2. charge injection figure 3. off isolation test circuit figure 4. r on test circuit 50% t r < 20ns t f < 20ns t off 90% v inh 0v v no v inl t on logic input switch input switch output 90% v out v out v (no or nc) r l r l r on () + ---------------------------- = switch input logic input v out r l c l com no or nc in 50 35pf gnd v+ c v out v out on off on q = v out x c l switch output logic input v inh v inl c l v out r g v g gnd com no or nc v+ c logic input in analyzer r l signal generator v+ c 0v or v+ no or nc com in gnd v+ c v inl or v inh no or nc com in gnd v nx v 1 r on = v 1 /100ma 100ma isl54054, ISL54055
7 fn6461.0 march 21, 2007 detailed description the intersil isl54054 and ISL54055 devices consist of low on-resistance, low voltage, bi-directional analog switches designed to operate from a single +1.8v to +5.5v supply. with a single supply of 5v the typical on-resistance is only 0.34 , with a typical turn-on and turn-off time of: t on = 12ns, t off = 12ns. the devices are especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8v), low power consumption (5.5 w), low leakage currents (300na max) and the tiny tdfn package. these devices have an unique architecture. they have two signal pins (pin 1 and pin 3) that are simultaneously connected or disconnected to a single common pin (pin 4) under the control of a single logic control pin (pin 6). the isl54054 switches are off when the logic is low and on when the logic is high. the ISL54055 are on when the logic is low and off when the logic is high. this architecture allows these devices to be used as a single spst switch or as a distribution switch to distribute a single source to two different loads. spst operation is achieved by us ing one of the nx signal pins while floating the other nx signal pin or by externally connecting the two nx signal pins together. when both signal pins are tied together, the r on of the spst is reduced by half, from 1 to 0.5 (when operated with a 5v supply). the isl54054 is a normally op en (no) spst an alog switch. the ISL54055 is a normally closed (nc) spst analog switch. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents, which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to gnd (see figure 6). to prevent forward biasing these diodes, v+ must be applied before any input signals, and the input signal voltages must remain between v+ and gnd. if these conditions cannot be guarant eed, then one of the following two protection methods should be employed. logic inputs can easily be protected by adding a 1k resistor in series with the input (see figure 6). the resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. this method is not acceptable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch. connecting schottky diodes to the signal pins (as shown in figure 6) will shunt the fault current to the supply or to ground, thereby protecting the switch. these schottky diodes must be sized to handle the expected fault current. figure 5. capacitance test circuit test circuits and waveforms (continued) v+ c gnd no or nc com in impedance analyzer v inl or v inh figure 6. overvoltage protection gnd v com v nx v+ in x optional protection resistor optional schottky diode optional schottky diode isl54054, ISL54055
8 fn6461.0 march 21, 2007 power-supply considerations the construction of the isl54054 and the ISL54055 is typical of most single supply cm os analog switches in that they have two supply pins: v+ and gnd. v+ and gnd drive the internal cmos switches and set their analog voltage limits. unlike switches with a 4.5v maximum supply voltage, the isl54054 and the ISL54055?s 5.5v maximum supply voltage provides plenty of room for the 10% tolerance of 4.5v supplies, as well as room for overshoot and noise spikes. the minimum recommended supply voltage is 1.8v. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to the electrical specification tables and typical performance curves on page for details. v+ and gnd also power the internal logic and level shiftier. the level shiftier converts the input logic levels to switched v+ and gnd signals to drive the analog switch gate terminals. this family of switches c annot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. logic-level thresholds this switch family is 1.8v logic compatible (0.5v and 1.4v) over a supply range of 2.5v to 5v (see figure 19). at 5v the v ih level is about 1.38v. this is still below the 1.8v cmos guaranteed high output minimum level of 1.4v, but noise margin is reduced. at 1.8v operation the v il level is around 0.1v and can only be used in 1. 8v applications with minimal ground bounce. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. driving the digital input signals from gn d to v+ with a fast transition time minimizes power dissipation. high-frequency performance in 50 s ystems, the isl54054 and the ISL54055 have a - 3db bandwidth of 72mhz with nx pins connected and 138mhz for a single nx input (see figure 20). the frequency response is very consistent over a wide v+ range, and for varying analog signal levels. an off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch?s input to its output. off isolation is the resistance to this feedthrough. figure 21 details the high off isolation rejection provided by this family. at 100khz, off isolation in 50 systems is about 74db with nx pins connected and 83db with a single nx input, decreasing approximately 20db per decade as frequency increases. higher load impedances decrease off isolation rejection due to the voltage divider action of the switch off impedance and the load impedance. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and gnd. one of these diodes conducts if any analog signal exceeds v+ or gnd. virtually all the analog leakage current comes from the esd diodes to v+ or gnd. although the esd diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or gnd and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and gnd pins constitutes the analog- signal-path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage curren ts of the same or opposite polarity. there is no connection between the analog signal paths and v+ or gnd. typical performance curves t a = +25 c, unless otherwise specified figure 7. on-resistance vs supply voltage vs switch voltage (nx pins connected) figure 8. on-resistance vs switch voltage (nx pins connected) r on ( ) v com (v) 01 23 4 0.2 0.3 0.4 0.5 0.6 1.2 v+ = 2.7v v+ = 1.8v v+ = 4.5v v+ = 3v i com = 100ma v+ = 5v 5 0.7 0.8 0.9 1.0 1.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 00.51.01.51.8 r on ( ) v com (v) +25c +85c -40c v+ = 1.8v i com = 100ma isl54054, ISL54055
9 fn6461.0 march 21, 2007 figure 9. on-resistance vs switch voltage (nx pins connected) figure 10. on-resistance vs switch voltage (nx pins connected) figure 11. on-resistance vs supply voltage vs switch voltage (single nx input) figure 12. on-resistance vs switch voltage (single nx input) figure 13. on-resistance vs switch voltage (single nx input) figure 14. on-resistance vs switch voltage (single nx input) typical performance curves t a = +25 c, unless otherwise specified (continued) r on ( ) v com (v) 0 0.51.01.52.02.53.0 v+ = 3v i com = 100ma 0.1 0.2 0.3 0.4 0.5 0.7 +25c +85c -40c 0.6 r on ( ) v com (v) 012345 i com = 100ma 0.05 0.10 0.15 0.20 0.25 0.45 +25c +85c -40c 0.30 0.35 0.40 v+ = 5v r on ( ) v com (v) 01234 0.5 0.7 0.9 1.1 1.3 2.3 v+ = 2.7v v+ = 1.8v v+ = 4.5v v+ = 3v i com = 100ma v+ = 5v 5 1.5 1.7 1.9 2.1 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 1.8 r on ( ) v com (v) +25c +85c -40c v+ = 1.8v i com = 100ma r on ( ) v com (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 v+ = 3v i com = 100ma 0.4 0.6 0.8 1.0 1.2 1.6 +25c +85c -40c 1.4 r on ( ) v com (v) 012345 v+ = 5v i com = 100ma 0.3 0.4 0.5 0.6 0.7 1.1 +25c -40c 0.8 0.9 1.0 +85c isl54054, ISL54055
10 fn6461.0 march 21, 2007 figure 15. turn on time vs supply voltage (isl54054) figure 16. turn off time vs supply voltage (isl54054) figure 17. turn on time vs supply voltage (ISL54055) figure 18. turn off time vs supply voltage (ISL54055) figure 19. digital switching point vs supp ly voltage figure 20. frequency response typical performance curves t a = +25 c, unless otherwise specified (continued) t on (ns) v+ (v) 5 10 15 20 25 30 -40c +85c +25c 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 t off (ns) v+ (v) 0 40 80 120 160 200 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 20 60 100 140 180 -40c +85c +25c t off (ns) v+ (v) 0 50 100 150 200 250 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40c 85c 25c t on (ns) v+ (v) 5 10 15 20 25 30 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40c +85c +25c v+ (v) v inh and v inl (v) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 5.5 v inh v inl frequency (hz) 0 -3 normalized gain (db) v+ = 5v 0.1k 10m 100m 500m v in = 0.2v p-p to 2.8v p-p r l = 50 -6 -9 1m single nx input nx pins connected isl54054, ISL54055
11 fn6461.0 march 21, 2007 die characteristics substrate potential (powered up): gnd transistor count: 57 process: submicron cmos figure 21. off isolation figure 22. charge injection vs switch voltage typical performance curves t a = +25 c, unless otherwise specified (continued) frequency (hz) 1k 100k 1m 100m 500m 10k 10m 110 10 20 30 40 50 60 70 80 90 100 v+ = 1.8v to 5.5v off isolation (db) v in = 1v p-p r l = 50 single nx input nx pins connected q (pc) v com (v) 0 0.5 1.0 2.0 2.5 3.0 5.0 0 20 40 80 100 120 140 v+ = 3v v+ = 5v v+ = 1.8v 1.5 3.5 4.0 4.5 60 isl54054, ISL54055
12 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6461.0 march 21, 2007 isl54054, ISL54055 ultra thin dual flat no-l ead plastic package (utdfn) b d a e 0.10 c 2x pin 1 top view 0.10 c 2x reference detail a 0.10 c 0.08 c 7x a3 a1 a c seating plane 5x l e 1 3 64 4x bottom view side view 0.10 cab 0.05 c b6x note 3 l1 detail a detail b pin 1 lead 0.1x45 chamfer detail b a3 a1 1.40 land pattern 1.00 0.30 0.35 0.20 0.45 0.40 0.20 10 l6.1.2x1.0a 6 lead ultra thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 0.95 1.00 1.05 - e 1.15 1.20 1.25 - e 0.40 bsc - l 0.30 0.35 0.40 - l1 0.40 0.45 0.50 - n 6 2 ne 3 3 0-12 4 rev. 2 8/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. ne refers to the number of terminals on e side. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389.

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